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| data sheet v1.2 2016-08 microcontrollers xmc ? 1400 aa-step microcontroller series for industrial applications xmc ? 1000 family arm ? cortex ? -m0 32-bit processor core
edition 2016-08 published by infineon technologies ag 81726 munich, germany ? 2016 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any ex amples or hints given herein, any typi cal values stated herein and/or any information regarding the application of the device, infi neon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-suppo rt devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. data sheet v1.2 2016-08 microcontrollers xmc ? 1400 aa-step microcontroller series for industrial applications xmc ? 1000 family arm ? cortex ? -m0 32-bit processor core xmc ? 1400 aa-step xmc ? 1000 family data sheet v1.2, 2016-08 trademarks c166?, tricore?, xmc? and dave? are trademarks of infineon technologies ag. arm ? , arm powered ? , cortex ? , thumb ? and amba ? are registered trademarks of arm, limited. coresight?, etm?, embedded trace macrocell? and embedded trace buffer? are trademarks of arm, limited. xmc1400 data sheet revision history: v1.2 2016-08 previous versions: v1.1 2016-06 v1.0 2016-02 v0.3 2015-10 page subjects many added xmc? trademark 10 , 12, 14 added xmc1402-t038x0200, xmc1402-q040x0200 and xmc1402-q048x0200 marking variants v1.1 2016-06 many added tssop-38-9 package 10 , 12, 14 added xmc1402-t038 marking variants in tssop-38 10 , 12, 14 added xmc1403-q040 marking variants v1.0 2016-02 9 the device provides four usic channels. 10 xmc1401 devices available for max. ambient temperature of 85c. 32 reformatted pinout table. 57 updated footnote to the definition of the start-up times of osc_xtal and rtc_xtal oscillators. 72 added f lt parameter to on-chip oscillators dco1 and dco2. 84 updated package outline drawings. we listen to your comments is there any information in this document that you feel is wrong, unclear or missing? your feedback will help us to continuousl y improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family table of contents data sheet 5 v1.2, 2016-08 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4 chip identification number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 general device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 pin configuration and definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.1 package pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.2 port pin for boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.3 port i/o function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.4 hardware controlled i/o function description . . . . . . . . . . . . . . . . . . . 31 3 electrical parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.1.1 parameter interpretati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.1.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.1.3 pin reliability in overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.1.4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.1 input/output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.2 analog to digital converters (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2.3 out of range comparator (orc) characteristics . . . . . . . . . . . . . . . . . 53 3.2.4 analog comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.2.5 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.2.6 oscillator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.7 power supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.2.8 flash memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.3 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.3.1 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.3.2 power-up and supply threshold characteristics . . . . . . . . . . . . . . . . . 70 3.3.3 on-chip oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.3.4 serial wire debug port (sw-dp) timing . . . . . . . . . . . . . . . . . . . . . . . . 73 3.3.5 spd timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.3.6 peripheral timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.3.6.1 synchronous serial interface (usic ssc) timing . . . . . . . . . . . . . . 75 3.3.6.2 inter-ic (iic) interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.3.6.3 inter-ic sound (iis) interface timing . . . . . . . . . . . . . . . . . . . . . . . . 80 4 package and reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.1 package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table of contents subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family table of contents data sheet 6 v1.2, 2016-08 4.1.1 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.2 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5 quality declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family about this document data sheet 7 v1.2, 2016-08 about this document this data sheet is addressed to embedded hardware and software developers. it provides the reader with detailed description s about the ordering designations, available features, electrical and physical characte ristics of the xmc1400 series devices. the document describes the characteristi cs of a superset of the xmc1400 series devices. for simplicity, the various device types are referred to by the collective term xmc1400 throughout this document. xmc ? 1000 family user documentation the set of user documentation includes: ? reference manual ? decribes the functionality of the superset of devices. ? data sheets ? list the complete ordering designations, available features and electrical characteristics of derivative devices. ? errata sheets ? list deviations from the specifications given in the related reference manual or data sheets. errata sheets are provided for the superset of devices. attention: please consult all parts of the documentation set to attain consolidated knowledge about your device. application related guidance is provided by users guides and application notes . please refer to http://www.infineon.com/xmc1000 to get access to the latest versions of those documents. subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family summary of features data sheet 8 v1.2, 2016-08 1 summary of features the xmc1400 devices are members of the xmc ? 1000 family of microcontrollers based on the arm cortex-m0 processor core. the xmc1400 series addresses the real-time control needs of motor control and digital po wer conversion. it also features peripherals for led lighting applications and human-machine interface (hmi). figure 1 block diagram ccu80 ccu81 posif0 posif1 ahb-lite bus math wdt scu apb bus prng ledts0 ledts1 ledts2 bccu0 flash 1 sram rom dts analog system anactrl 2 x dco evr ahb to apb bridge pau acmp & orc ports rtc eru0 usic1 usic0 vadc ccu40 ccu41 multican+ eru1 debug system swd cpu arm ? cortex ? ? m0 nvic spd subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family data sheet 9 v1.2, 2016-08 features cpu subsystem ? 32-bit arm cortex-m0 cpu core ? 0.84 dmips/mhz (dhrystone 2.1) at 48 mhz ? nested vectored interrupt controller ? 64 interrupt nodes ? math coprocessor ? 24-bit trigonometric calculation (cordic) ? 32-bit divide operation ? 2x4 channels eru for event interconnections on-chip memories ? 8 kbyte rom ? 16 kbyte sram (with parity) ? up to 200 kbyte flash (with ecc) supply, reset and clock ? 1.8 v to 5.5 v supply with power on reset and brownout detector ? on-chip clock monitor ? external crystal oscillator support (32 khz and 4 to 20 mhz) ? internal slow and fast oscillators without the need of pll system control ? window watchdog ? real time clock module ? pseudo random number generator communication peripherals ? four usic channels, usable as ? uart (up to 12 mb/s) ? single-spi (up to 12 mb/s) ? double-spi (up to 2 analog frontend peripherals ? a/d converters (up to 12 analog inputs) ? 2 sample and hold stages ? fast 12-bit adc (up to 1.1 ms/s), adjustable gain ? 0 v to 5.5 v input range ? up to 8 channels out of range comparators ? up to 4 fast analog comparators ? temperature sensor industrial control peripherals ? 2x4 16-bit 96 mhz ccu4 timers for signal monitoring and pwm ? 2x4 16-bit 96 mhz ccu8 timers for complex pwm, complementary high/low side switches and multi phase control ? 2x posif for hall and quadrature encoders, motor positioning ? 9 channel bccu (brightness and color control) for led li ghting applications up to 56 input/output ports ? 1.8 v to 5.5 v capable ? up to 8 high current pads (50 ma sink) on-chip debug support ? 4 breakpoints, 2 watchpoints ? arm serial wire debug, single-pin debug interfaces programming support ? single-pin bootloader ? secure bootstrap loader sbsl (optional) packages ? tssop-38 (9.7 tools ? free dave? toolchain with low level drivers and apps subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family data sheet 10 v1.2, 2016-08 1.1 device overview the following table lists the available featur es per device type for the xmc1400 series. table 1 features of xmc1400 device types 1) features xmc1401-q048 xmc1401-f064 xmc1402-t038 xmc1402-q040 xmc1402-q048 xmc1402-q064 xmc1402-f064 xmc1403-q040 xmc1403-q048 xmc1403-q064 xmc1404-q048 xmc1404-q064 xmc1404-f064 cpu frequency 48 mhz operating temperature (ambient) -40 to 85 c -40 to 105 c operating voltage 1.8 v to 5.5 v flash options (kbytes) 64, 128 64, 128 32, 64, 128 200 32, 64, 128 200 32, 64, 128 200 64, 128 200 64, 128 200 64, 128 200 64, 128 200 64, 128 200 64, 128 200 64, 128 200 64, 128 200 sram (kbytes) 16 16 16 16 16 16 16 16 16 16 16 16 16 math --11111---111 industrial control ccu4 2222222222222 ccu8 - - 2 2 222- - - 222 posif --11222---222 bccu --11111---111 communication usic (modules / channels) 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 2/ 2 ledts 33--------333 multican+ (nodes / mos) -------2/ 32 2/ 32 2/ 32 2/ 32 2/ 32 2/ 32 subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family data sheet 11 v1.2, 2016-08 1.2 ordering information the ordering code for an infineon microcontroller provides an exact reference to a specific product. the code ?xmc1< ddd>- xmc ? 1400 aa-step xmc ? 1000 family data sheet 12 v1.2, 2016-08 1.3 device types these device types are available and can be ordered through infineon?s direct and/or distribution channels. table 2 synopsis of xmc1400 device types derivative package flash kbytes xmc1401-q048f0064 pg-vqfn-48 64 xmc1401-q048f0128 pg-vqfn-48 128 xmc1401-f064f0064 pg-lqfp-64 64 xmc1401-f064f0128 pg-lqfp-64 128 xmc1402-t038x0032 pg-tssop-38 32 xmc1402-t038x0064 pg-tssop-38 64 xmc1402-t038x0128 pg-tssop-38 128 xmc1402-t038x0128 pg-tssop-38 200 XMC1402-Q040X0032 pg-vqfn-40 32 xmc1402-q040x0064 pg-vqfn-40 64 xmc1402-q040x0128 pg-vqfn-40 128 xmc1402-q040x0200 pg-vqfn-40 200 xmc1402-q048x0032 pg-vqfn-48 32 xmc1402-q048x0064 pg-vqfn-48 64 xmc1402-q048x0128 pg-vqfn-48 128 xmc1402-q048x0128 pg-vqfn-48 200 xmc1402-q064x0064 pg-vqfn-64 64 xmc1402-q064x0128 pg-vqfn-64 128 xmc1402-q064x0200 pg-vqfn-64 200 xmc1402-f064x0064 pg-lqfp-64 64 xmc1402-f064x0128 pg-lqfp-64 128 xmc1402-f064x0200 pg-lqfp-64 200 xmc1403-q040x0064 pg-vqfn-40 64 xmc1403-q040x0128 pg-vqfn-40 128 xmc1403-q040x0200 pg-vqfn-40 200 xmc1403-q048x0064 pg-vqfn-48 64 xmc1403-q048x0128 pg-vqfn-48 128 subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family data sheet 13 v1.2, 2016-08 xmc1403-q048x0200 pg-vqfn-48 200 xmc1403-q064x0064 pg-vqfn-64 64 xmc1403-q064x0128 pg-vqfn-64 128 xmc1403-q064x0200 pg-vqfn-64 200 xmc1404-q048x0064 pg-vqfn-48 64 xmc1404-q048x0128 pg-vqfn-48 128 xmc1404-q048x0200 pg-vqfn-48 200 xmc1404-q064x0064 pg-vqfn-64 64 xmc1404-q064x0128 pg-vqfn-64 128 xmc1404-q064x0200 pg-vqfn-64 200 xmc1404-f064x0064 pg-lqfp-64 64 xmc1404-f064x0128 pg-lqfp-64 128 xmc1404-f064x0200 pg-lqfp-64 200 table 2 synopsis of xmc1400 device types (cont?d) derivative package flash kbytes subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family data sheet 14 v1.2, 2016-08 1.4 chip identification number the chip identification number allows software to identify the marking. it is an 8 words value with the most significant 7 words stor ed in flash configuration sector 0 (cs0) at address location : 1000 0f00 h (msb) - 1000 0f1b h (lsb). the least significant word and most significant word of the chip identi fication number are the value of registers dbgromid and idchip, respectively. table 3 xmc1400 chip identification number derivative value marking xmc1401-q048f0064 00014082 07cf00ff 1e071ff7 20006000 00000d00 00001000 00011000 10204083 h aa xmc1401-q048f0128 00014082 07cf00ff 1e071ff7 20006000 00000d00 00001000 00021000 10204083 h aa xmc1401-f064f0064 000140a2 07cf00ff 1e071ff7 20006000 00000d00 00001000 00011000 10204083 h aa xmc1401-f064f0128 000140a2 07cf00ff 1e071ff7 20006000 00000d00 00001000 00021000 10204083 h aa xmc1402-t038x0032 00014013 07ff00ff 1e071ff7 000f900f 00000d00 00001000 00009000 10204083 h aa xmc1402-t038x0064 00014013 07ff00ff 1e071ff7 000f900f 00000d00 00001000 00011000 10204083 h aa xmc1402-t038x0128 00014013 07ff00ff 1e071ff7 000f900f 00000d00 00001000 00021000 10204083 h aa xmc1402-t038x0200 00014013 07ff00ff 1e071ff7 000f900f 00000d00 00001000 00033000 10204083 h aa XMC1402-Q040X0032 00014043 07ff00ff 1e071ff7 000f900f 00000d00 00001000 00009000 10204083 h aa xmc1402-q040x0064 00014043 07ff00ff 1e071ff7 000f900f 00000d00 00001000 00011000 10204083 h aa xmc1402-q040x0128 00014043 07ff00ff 1e071ff7 000f900f 00000d00 00001000 00021000 10204083 h aa xmc1402-q040x0200 00014043 07ff00ff 1e071ff7 000f900f 00000d00 00001000 00033000 10204083 h aa xmc1402-q048x0032 00014083 07ff00ff 1e071ff7 100f900f 00000d00 00001000 00009000 10204083 h aa subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family data sheet 15 v1.2, 2016-08 xmc1402-q048x0064 00014083 07ff00ff 1e071ff7 100f900f 00000d00 00001000 00011000 10204083 h aa xmc1402-q048x0128 00014083 07ff00ff 1e071ff7 100f900f 00000d00 00001000 00021000 10204083 h aa xmc1402-q048x0200 00014083 07ff00ff 1e071ff7 100f900f 00000d00 00001000 00033000 10204083 h aa xmc1402-q064x0064 00014093 07ff00ff 1e071ff7 100f900f 00000d00 00001000 00011000 10204083 h aa xmc1402-q064x0128 00014093 07ff00ff 1e071ff7 100f900f 00000d00 00001000 00021000 10204083 h aa xmc1402-q064x0200 00014093 07ff00ff 1e071ff7 100f900f 00000d00 00001000 00033000 10204083 h aa xmc1402-f064x0064 000140a3 07ff00ff 1e071ff7 100f900f 00000d00 00001000 00011000 10204083 h aa xmc1402-f064x0128 000140a3 07ff00ff 1e071ff7 100f900f 00000d00 00001000 00021000 10204083 h aa xmc1402-f064x0200 000140a3 07ff00ff 1e071ff7 100f900f 00000d00 00001000 00033000 10204083 h aa xmc1403-q040x0064 00014043 07cf00ff 1e071ff7 00b00000 00000d00 00001000 00011000 10204083 h aa xmc1403-q040x0128 00014043 07cf00ff 1e071ff7 00b00000 00000d00 00001000 00021000 10204083 h aa xmc1403-q040x0200 00014043 07cf00ff 1e071ff7 00b00000 00000d00 00001000 00033000 10204083 h aa xmc1403-q048x0064 00014083 07cf00ff 1e071ff7 00b00000 00000d00 00001000 00011000 10204083 h aa xmc1403-q048x0128 00014083 07cf00ff 1e071ff7 00b00000 00000d00 00001000 00021000 10204083 h aa xmc1403-q048x0200 00014083 07cf00ff 1e071ff7 00b00000 00000d00 00001000 00033000 10204083 h aa xmc1403-q064x0064 00014093 07cf00ff 1e071ff7 00b00000 00000d00 00001000 00011000 10204083 h aa xmc1403-q064x0128 00014093 07cf00ff 1e071ff7 00b00000 00000d00 00001000 00021000 10204083 h aa table 3 xmc1400 chip identification number (cont?d) derivative value marking subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family data sheet 16 v1.2, 2016-08 xmc1403-q064x0200 00014093 07cf00ff 1e071ff7 00b00000 00000d00 00001000 00033000 10204083 h aa xmc1404-q048x0064 00014083 07ff00ff 1e071ff7 30bff00f 00000d00 00001000 00011000 10204083 h aa xmc1404-q048x0128 00014083 07ff00ff 1e071ff7 30bff00f 00000d00 00001000 00021000 10204083 h aa xmc1404-q048x0200 00014083 07ff00ff 1e071ff7 30bff00f 00000d00 00001000 00033000 10204083 h aa xmc1404-q064x0064 00014093 07ff00ff 1e071ff7 30bff00f 00000d00 00001000 00011000 10204083 h aa xmc1404-q064x0128 00014093 07ff00ff 1e071ff7 30bff00f 00000d00 00001000 00021000 10204083 h aa xmc1404-q064x0200 00014093 07ff00ff 1e071ff7 30bff00f 00000d00 00001000 00033000 10204083 h aa xmc1404-f064x0064 000140a3 07ff00ff 1e071ff7 30bff00f 00000d00 00001000 00011000 10204083 h aa xmc1404-f064x0128 000140a3 07ff00ff 1e071ff7 30bff00f 00000d00 00001000 00021000 10204083 h aa xmc1404-f064x0200 000140a3 07ff00ff 1e071ff7 30bff00f 00000d00 00001000 00033000 10204083 h aa table 3 xmc1400 chip identification number (cont?d) derivative value marking subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family general device information data sheet 17 v1.2, 2016-08 2 general device information this section summarizes the logic symbols and package pin configurations with a detailed list of the functional i/o mapping. 2.1 logic symbols figure 2 xmc1400 logic symbol for tssop-38-9 xmc1400 tssop-38 port 0 12 bit v ddp (2) v ssp (2) port 0 / xtal 4 bit port 1 / high-current 6bit port 2 / analog input 4 bit port 2 / analog input 8 bit subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family general device information data sheet 18 v1.2, 2016-08 figure 3 xmc1400 logic symbol for pg-vqfn-40-17 xmc1400 vqfn-40 v dd (1) v ss (1) port 0 12 bit v ddp (2) v ssp (1) port 0 / xtal 4 bit port 1 / high-current 7 bit port 2 / analog input 4 bit port 2 / analog input 8 bit exp. die pad ( v ssp ) subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family general device information data sheet 19 v1.2, 2016-08 figure 4 xmc1400 logic symbol for pg-vqfn-48-73 xmc1400 vqfn-48 v dd (1) v ss (1) port 0 12 bit v ddp (3) v ssp (1) port 2 / analog input 6 bit port 2 / analog input 8 bit port 3 1 bit port 4 4 bit port 0 / xtal 4 bit exp. die pad ( v ssp ) port 1 / high-current 7 bit subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family general device information data sheet 20 v1.2, 2016-08 figure 5 xmc1400 logic symbol fo r pg-lqfp-64-26 / pg-vqfn-64-6 xmc1400 vqfn-64 / lqfp-64 v dd (1) v ss (1) v ddp (4) v ssp (2) port 1 / high-current 8 bit port 1 1 bit port 0 12 bit port 0 / xtal 4 bit exp. die pad ( v ssp ) 1) 1) vqfn64 only port 2 / analog input 6 bit port 2 / analog input 8 bit port 3 5 bit port 4 12 bit subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family general device information data sheet 21 v1.2, 2016-08 2.2 pin configuration and definition the following figures summarize all pins, showing their locations on the different packages. figure 6 xmc1400 pg-tssop-38-9 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 37 36 35 34 33 32 31 30 29 38 p2.5 p2.6 p2.7 p0.10 v ssp /v ss v ddp /v dd p0.13 p0.14 p2.1 p2.0 p2.2 p0.11 p0.12 p1.4 p0.8 p0.9 p2.10 p2.9 p2.3 p2.4 p2.11 v ddp p1.3 p1.2 v ssp 15 16 17 18 19 24 23 22 21 20 p2.8 p1.5 p1.0 p0.0 p0.1 p1.1 p0.2 p0.6 p0.7 p0.4 p0.5 p0.3 p0.15 top view subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family general device information data sheet 22 v1.2, 2016-08 figure 7 xmc1400 pg-vqfn-40-17 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 13 14 15 24 23 22 21 20 19 18 17 16 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 p0 .1 3 p0.12 analog input / p2.0 v dd p v ssp p0.1 p0.2 p0.0 12 analog input / p2.1 analog input / p2.2 analog input / p2.3 analog input / p2.4 analog input / p2.5 analog input / p2.6 analog input / p2.7 analog input / p2.8 analog input / p2.9 analog input / p2.10 analog input / p2.11 p1.2 / high -cu rre nt p0 .6 p0 .7 p0 .5 p0 .3 p0 .4 p0 .1 5 p0 .14 p0.8 / rtc_xtal1 p0.9 / rtc_xtal2 p0.10 / xtal1 p0.11 / xtal2 v ddp v ss v dd p1.0 / high-current p1.1 / high-current p1.3 / high -cu rre nt p1.4 / high -cu rre nt p1.5 / high -cu rre nt p1.6 / high -cu rre nt subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family general device information data sheet 23 v1.2, 2016-08 figure 8 xmc1400 pg-vqfn-48-73 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 45 46 47 48 p0.13 p0 .12 p4.6 v ddp v ssp p4.7 analog input / p2.0 analog input / p2.1 analog input / p2.2 analog input / p2.3 analog input / p2.4 analog input / p2.5 analog input / p2.6 analog input / p2.7 p0.15 p0.14 11 12 analog input / p2.8 analog input / p2.9 13 15 16 17 20 19 18 14 22 21 24 23 analog input / p2.12 analog input / p2.13 28 27 26 25 32 31 30 29 34 33 36 35 p0.6 p0.7 p3.0 p0.1 p0.2 p0.0 p0.5 p0.3 p0.4 v ddp 38 37 p4.4 p4 .5 p0.8 / rtc_xtal1 p0.9 / rtc_xtal2 p0.10 / xtal1 p0.11 / xtal2 v ddp v ss v dd p1.0 / high-current p1.1 / high-current p1.2 / high-current p1.3 / high-current p1.4 / high-current p1.5 / high-current p1.6 / high-current analog input / p2.10 analog input / p2.11 subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family general device information data sheet 24 v1.2, 2016-08 figure 9 xmc1400 pg-lqfp-64-26 / pg-vqfn-64-6 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 60 59 58 57 56 55 61 62 63 64 p0.13 p0 .12 p4 .6 p4.7 p0 .15 p0.14 11 12 54 53 p4.0 p4.1 13 14 15 16 17 19 20 21 24 23 22 18 26 25 28 27 36 35 34 33 40 39 38 37 42 41 44 43 p0.2 p0.3 p3.0 p3.2 p3.3 p3.1 p0.1 p3.4 p0.0 v ddp 30 29 32 31 46 45 p0.4 p0.5 48 47 p0.6 p0.7 50 49 52 51 p0.8 / rtc_xtal1 v ssp v ddp p4.8 p4.9 p4.10 p4.11 analog input / p2.8 p1.8 p1.7 / high-current v ssp v ddp p4.2 p4.3 p4.4 p4.5 p0.9 / rtc_xtal2 p0.10 / xtal1 p0.11 / xtal2 v ddp v ss v dd p1.0 / high-current p1.1 / high-current p1.2 / high-current p1.3 / high-current p1.4 / high-current p1.5 / high-current p1.6 / high-current analog input / p2.0 analog input / p2.1 analog input / p2.2 analog input / p2.3 analog input / p2.4 analog input / p2.5 analog input / p2.6 analog input / p2.7 analog input / p2.9 analog input / p2.10 analog input / p2.11 analog input / p2.12 analog input / p2.13 subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family general device information data sheet 25 v1.2, 2016-08 2.2.1 package pin summary the following general building block is used to describe each pin: the table is sorted by the ?function? column, starting with the regular port pins (px.y), followed by the supply pins. the following columns, titled with the supported package variants, lists the package pin number to which the respective function is mapped in that package. the ?pad type? indicates the employed pad type: ? std_inout (standard bi-directional pads) ? std_inout/an (standard bi-directional pads with analog input) ? std_inout/clock (standard bi-directi onal pads with oscillator function) ? high current (high current bi-directional pads) ? std_in/an (standard input pads with analog input) ? power (power supply) details about the pad properties are defin ed in the electrical parameter chapter. table 4 package pin mapping description function package a package b ... pad type px.y n n pad class table 5 package pin mapping function lqfp 64, vqfn 64 vqfn 48 vqfn 40 tssop 38 pad type notes p0.0 41 29 23 17 std_inout p0.1 42 30 24 18 std_inout p0.2 43 31 25 19 std_inout p0.3 44 32 26 20 std_inout p0.4 45 33 27 21 std_inout p0.5 46 34 28 22 std_inout p0.6 47 35 29 23 std_inout p0.7 48 36 30 24 std_inout p0.8/ rtc_ xtal1 51 39 33 27 std_inout /clock_in subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family general device information data sheet 26 v1.2, 2016-08 p0.9/ rtc_ xtal2 52 40 34 28 std_inout /clock_o p0.10/ xtal1 53 41 35 29 std_inout /clock_in p0.11/ xtal2 54 42 36 30 std_inout /clock_o p0.1255433731std_inout p0.1356443832std_inout p0.1457453933std_inout p0.1558464034std_inout p1.0 34 26 22 16 high current p1.1 33 25 21 15 high current p1.2 32 24 20 14 high current p1.3 31 23 19 13 high current p1.4 30 22 18 12 high current p1.5 29 21 17 11 high current p1.6 28 20 16 - high current p1.7 27 - - - high current p1.8 26 - - - std_inout p2.0 9 3 1 35 std_inout /an p2.1 10 4 2 36 std_inout /an p2.2 11 5 3 37 std_in/an p2.3 12 6 4 38 std_in/an p2.4 13 7 5 1 std_in/an p2.5 14 8 6 2 std_in/an p2.6 15 9 7 3 std_in/an p2.7 16 10 8 4 std_in/an table 5 package pin mapping (cont?d) function lqfp 64, vqfn 64 vqfn 48 vqfn 40 tssop 38 pad type notes subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family general device information data sheet 27 v1.2, 2016-08 p2.8 17 11 9 5 std_in/an p2.9 18 12 10 6 std_in/an p2.10 19 13 11 7 std_inout /an p2.11 20 14 12 8 std_inout /an p2.12 21 15 - - std_inout /an p2.13 22 16 - - std_inout /an p3.0 36 28 - - std_inout p3.1 37 - - - std_inout p3.2 38 - - - std_inout p3.3 39 - - - std_inout p3.4 40 - - - std_inout p4.0 59 - - - std_inout p4.1 60 - - - std_inout p4.2 61 - - - std_inout p4.3 62 - - - std_inout p4.4 63 47 - - std_inout p4.5 64 48 - - std_inout p4.6 3 1 - - std_inout p4.7 4 2 - - std_inout p4.8 5 - - - std_inout p4.9 6 - - - std_inout p4.10 7 - - - std_inout p4.11 8 - - - std_inout vss 23 17 13 9 power supply gnd, adc reference gnd table 5 package pin mapping (cont?d) function lqfp 64, vqfn 64 vqfn 48 vqfn 40 tssop 38 pad type notes subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family general device information data sheet 28 v1.2, 2016-08 vdd 24 18 14 10 power supply vdd, adc reference voltage/ orc reference voltage vddp 25 19 15 10 power when vdd is supplied, vddp has to be supplied with the same voltage. vddp 2 - - - power i/o port supply vddp 35 27 - - power i/o port supply vddp 50 38 32 26 power i/o port supply vssp 1 - - - power i/o port ground vssp 49 37 31 25 power i/o port ground vssp exp. pad (in vqfn 64 only) exp. pad exp. pad - power exposed die pad the exposed die pad is connected internally to vssp. for proper operation, it is mandatory to connect the exposed pad to the board ground. for thermal aspects, please refer to the package and reliability chapter. table 5 package pin mapping (cont?d) function lqfp 64, vqfn 64 vqfn 48 vqfn 40 tssop 38 pad type notes subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family general device information data sheet 29 v1.2, 2016-08 2.2.2 port pin for boot modes port functions can be overruled by the boot mode selected. the type of boot mode is selected via bmi. table 6 shows the port pins used for the various boot modes. table 6 port pin for boot modes pin boot boot description p0.13 cs(o) ssc bsl mode p0.14 swdio_0 debug mode (swd) spd_0 debug mode (spd) rx/tx asc bsl half-duplex mode rx asc bsl full-duplex mode rx can bsl mode sclk(o) ssc bsl mode p0.15 swdclk_0 debug mode (swd) tx asc bsl full-duplex mode tx can bsl mode data(i/o) ssc bsl mode p1.2 swdclk_1 debug mode (swd) tx asc bsl full-duplex mode tx can bsl mode p1.3 swdio_1 debug mode (swd) spd_1 debug mode (spd) rx/tx asc bsl half-duplex mode rx asc bsl full-duplex mode rx can bsl mode p4.6 hwcon0 boot pins (boot from pins mode must be selected) p4.7 hwcon1 subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family general device information data sheet 30 v1.2, 2016-08 2.2.3 port i/o function description the following general building block is used to describe the i/o functions of each port pin: figure 10 simplified port structure pn.y is the port pin name, defining the cont rol and data bits/registers associated with it. as gpio, the port is under software control. its input value is read via pn_in.y, pn_out defines the output value. up to nine alternate output functions (alt1 to alt9) can be mapped to a single port pin, selected by pn_iocr.pc. the output value is directly driven by the respective module, with the pin characteristics controlled by th e port registers (wit hin the limits of the connected pad). the port pin input can be connected to mult iple peripherals. most peripherals have an input multiplexer to select between different possible input sources. the input path is also active while the pin is configured as output. th is allows to feedback an output to on-chip resources witho ut wasting an additional external pin. please refer to the port i/o functions table for the complete port i/o function mapping. table 7 port i/o function description function outputs inputs alt1 altn input input p0.0 moda.out modc.ina pn.y moda.out moda.ina modc.inb xmc1000 pn.y v ddp gnd pn.y alt1 ... altn hwo0 hwo1 sw control logic input 0 input n ... pad hwi0 hwi1 modb.out modb moda moda.ina subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family general device information data sheet 31 v1.2, 2016-08 2.2.4 hardware controlled i/o function description the following general building block is used to describe the hardware i/o and pull control functions of each port pin: by pn_hwsel, it is possible to select between different hardware ?masters? (hwo0/hwi0, hwo1/hwi1). the selected peri pheral can take control of the pin(s). hardware control overrules se ttings in the respective port pin registers. additional hardware signals hw0_pd/hw1_pd a nd hw0_pu/hw1_pu controlled by the peripherals can be used to cont rol the pull devices of the pin. please refer to the hardware controlled i/o functions table for the complete hardware i/o and pull control function mapping. table 8 hardware controlled i/o function description function outputs inputs pull control hwo0 hwi0 hw0_pd hw0_pu p0.0 modb.out modb.ina pn.y modc.out modc.out subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family data sheet 32 v1.2, 2016-08 port i/o function table table 9 port i/o functions function outputs inputs alt1 alt2 alt3 alt4 alt5 alt6 alt7 alt8 alt9 input input input input input input input input input input input input p0.0 eru0.p dout0 ledts0 .line7 eru0.g out0 ccu40. out0 ccu80. out00 usic0_ ch0.se lo0 usic0_ ch1.se lo0 ccu81. out00 usic1_ ch1.do ut0 bccu0. trapin b ccu40.i n0ac usic1_ ch1.dx 0a usic0_ ch0.d x2a usic0_ ch1.dx 2a p0.1 eru0.p dout1 ledts0 .line6 eru0.g out1 ccu40. out1 ccu80. out01 bccu0. out8 scu.vd rop usic1_ ch1.sc lkout usic1_ ch1.do ut0 ccu40.i n1ac usic1_ ch1.dx 0b usic1_ ch1.d x1a p0.2 eru0.p dout2 ledts0 .line5 eru0.g out2 ccu40. out2 ccu80. out02 vadc0. emux02 ccu80. out10 usic1_ ch0.sc lkout usic1_ ch0.do ut0 ccu40.i n2ac usic1_ ch0.dx 0a usic1_ ch0.d x1a p0.3 eru0.p dout3 ledts0 .line4 eru0.g ou t 3 ccu40. out3 ccu80. out03 vadc0. emux01 ccu80. out11 usic1_ ch1.sc lkout usic1_ ch0.do ut0 ccu40.i n3ac usic1_ ch0.dx 0b p0.4 bccu0. out0 ledts0 .line3 ledts0 .col3 ccu40. out1 ccu80. out13 vadc0. emux00 wwdt. servic e_out usic1_ ch1.se lo0 can.n0 _txd ccu41.i n0ab ccu80.i n0ab can.n0 _rxda p0.5 bccu0. out1 ledts0 .line2 ledts0 .col2 ccu40. out0 ccu80. out12 acmp2. out ccu80. out01 vadc0. emux10 can.n0 _txd ccu41.i n1ab ccu80.i n1ab can.n0 _rxdb p0.6 bccu0. out2 ledts0 .line1 ledts0 .col1 ccu40. out0 ccu80. out11 usic0_ ch1.mc lkout usic0_ ch1.do ut0 vadc0. emux11 ccu41. out0 ccu40.i n0ab ccu41.i n2ab usic0_ ch1.dx 0c p0.7 bccu0. ou t 3 ledts0 .line0 ledts0 .col0 ccu40. out1 ccu80. out10 usic0_ ch0.sc lkout usic0_ ch1.do ut0 vadc0. emux12 ccu41. out1 ccu40.i n1ab ccu41.i n3ab usic0_ ch0.d x1c usic0_ ch1.dx 0d usic0_ ch1.dx 1c p0.8/ rtc_xtal1 bccu0. out4 ledts1 .line0 ledts0 .cola ccu40. out2 ccu80. out20 usic0_ ch0.sc lkout usic0_ ch1.sc lkout ccu81. out20 ccu41. out2 ccu40.i n2ab usic0_ ch0.d x1b usic0_ ch1.dx 1b p0.9/ rtc_xtal2 bccu0. out5 ledts1 .line1 ledts0 .col6 ccu40. out3 ccu80. out21 usic0_ ch0.se lo0 usic0_ ch1.se lo0 ccu81. out21 ccu41. out3 ccu40.i n3ab usic0_ ch0.d x2b usic0_ ch1.dx 2b p0.10/ xtal1 bccu0. out6 ledts1 .line2 ledts0 .col5 acmp0. ou t ccu8 0. out22 usic0_ ch0.se lo1 usic0_ ch1.se lo1 ccu81. out22 ccu80.i n2ab ccu81.i n2ab usic0_ ch0.d x2c usic0_ ch1.dx 2c p0.11/ xtal2 bccu0. out7 ledts1 .line3 ledts0 .col4 usic0_ ch0.mc lkout ccu80. out23 usic0_ ch0.se lo2 usic0_ ch1.se lo2 ccu81. out23 usic0_ ch0.d x2d usic0_ ch1.dx 2d p0.12 bccu0. out6 ledts1 .line4 ledts0 .col3 ledts1 .col3 ccu80. out33 usic0_ ch0.se lo3 ccu80. out20 can.n1 _txd bccu0. trapin a ccu40.i n0aa ccu40.i n1aa ccu40.i n2aa ccu81.i n0au ccu40.i n3aa ccu80.i n0aa usic0_ ch0.d x2e ccu80.i n1aa ccu80.i n2aa can.n1 _rxda ccu80.i n3aa subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family data sheet 33 v1.2, 2016-08 p0.13 wwdt. servic e_out ledts1 .line5 ledts0 .col2 ledts1 .col2 ccu80. out32 usic0_ ch0.se lo4 ccu80. out21 can.n1 _txd ccu80.i n3ab ccu81.i n1au posif0. in0b usic0_ ch0.d x2f can.n1 _rxdb p0.14 bccu0. out7 ledts1 .line6 ledts0 .col1 ledts1 .col1 ccu80. out31 usic0_ ch0.do ut0 usic0_ ch0.sc lkout can.n0 _txd ccu81.i n2au posif0. in1b usic0_ ch0.dx 0a usic0_ ch0.d x1a usic1_ ch1.dx 5b can.n0 _rxdc p0.15 bccu0. out8 ledts1 .line7 ledts0 .col0 ledts1 .col0 ccu80. out30 usic0_ ch0.do ut0 usic0_ ch1.mc lkout can.n0 _txd ccu81.i n3au posif0. in2b usic0_ ch0.dx 0b usic1_ ch1.dx 3b usic1_ ch1.dx 4b can.n0 _rxdd p1.0 bccu0. out0 ccu40. out0 ledts0 .col0 ledts1 .cola ccu80. out00 acmp1. out usic0_ ch0.do ut0 ccu81. ou t 00 can.n0 _txd posif0. in2a usic0_ ch0.dx 0c can.n0 _rxdg p1.1 eru1.p dout1 ccu40. out1 ledts0 .col1 ledts1 .col0 ccu80. out01 usic0_ ch0.do ut0 usic0_ ch1.se lo0 ccu81. out01 can.n0 _txd posif0. in1a usic0_ ch0.dx 0d usic0_ ch0.d x1d usic0_ ch1.dx 2e can.n0 _rxdh p1.2 eru1.p dout2 ccu40. out2 ledts0 .col2 ledts1 .col1 ccu80. out10 acmp2. out usic0_ ch1.do ut0 ccu81. out10 can.n1 _txd posif0. in0a usic0_ ch1.dx 0b can.n1 _rxdg p1.3 eru1.p dout3 ccu40. out3 ledts0 .col3 ledts1 .col2 ccu80. out11 usic0_ ch1.sc lkout usic0_ ch1.do ut0 ccu81. out11 can.n1 _txd usic0_ ch1.dx 0a usic0_ ch1.dx 1a can.n1 _rxdh p1.4 er u 1.p dout0 usic0_ ch1.sc lkout ledts0 .col4 ledts1 .col3 ccu80. out20 usic0_ ch0.se lo0 usic0_ ch1.se lo1 ccu81. out20 ccu41. out0 usic0_ ch0.dx 5e usic0_ ch1.dx 5e p1.5 eru1.p dout1 usic0_ ch0.do ut0 ledts0 .cola bccu0. out1 ccu80. out21 usic0_ ch0.se lo1 usic0_ ch1.se lo2 ccu81. out21 ccu41. out1 usic0_ ch1.dx 5f p1.6 eru1.p dout2 usic0_ ch1.do ut0 ledts0 .col5 usic0_ ch0.sc lkout bccu0. out2 usic0_ ch0.se lo2 usic0_ ch1.se lo3 ccu81. out30 ccu41. out2 posif1. in2a usic0_ ch0.dx 5f p1.7 bccu0. out8 ccu40. out3 ledts0 .col6 ledts1 .col4 acmp3. out eru1.p dout3 ccu81. out31 ccu41. out3 posif1. in1a usic1_ ch0.dx 5b us ic1 _ ch1.dx 2c p1.8 bccu0. out0 ccu40. out0 usic1_ ch1.sc lkout vadc0. emux02 acmp1. out eru1.p dout0 ccu81. out32 posif1. in0a usic1_ ch0.dx 3b usic1_ ch0.d x4b usic1_ ch1.dx 1c p2.0 eru0.p dout3 ccu40. out0 eru0.g out3 ledts1 .col5 ccu80. out20 usic0_ ch0.do ut0 usic0_ ch0.sc lkout ccu81. out20 can.n0 _txd vadc0. g0ch5 usic0_ ch0.dx 0e usic0_ ch0.d x1e usic0_ ch1.dx 2f can.n0 _rxde eru0.0 b0 p2.1 eru0.p dout2 ccu40. out1 eru0.g out2 ledts1 .col6 ccu80. out21 usic0_ ch0.do ut0 usic0_ ch1.sc lkout ccu81. out21 can.n0 _txd acmp2.i np vadc0. g0ch6 usic0_ ch0.dx 0f usic0_ ch1.dx 3a usic0_ ch1.dx 4a ca n.n0 _r xdf eru0.1 b0 table 9 port i/o functions (cont?d) function outputs inputs alt1 alt2 alt3 alt4 alt5 alt6 alt7 alt8 alt9 input input input input input input input input input input input input subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family data sheet 34 v1.2, 2016-08 p2.2 acmp2.i nn vadc0. g0ch7 orc0.ai n usic1_ ch0.dx 5e usic0_ ch0.dx 3a usic0_ ch0.d x4a usic0_ ch1.dx 5a eru0.0 b1 p2.3 vadc0. g1ch5 orc1.ai n usic1_ ch0.dx 3e usic1_ ch0.dx 4e usic1_ ch1.dx 5c usic0_ ch0.d x5b usic0_ ch1.dx 3c usic0_ ch1.dx 4c eru0.1 b1 p2.4 vadc0. g1ch6 orc2.ai n usic1_ ch1.dx 3c usic1_ ch1.dx 4c usic0_ ch0.dx 3b usic0_ ch0.d x4b usic1_ ch0.dx 5f usic0_ ch1.dx 5b eru0.0 a1 p2.5 vadc0. g1ch7 orc3.ai n usic1_ ch1.dx 5d usic0_ ch0.dx 5d usic0_ ch1.dx 3e usic0_ ch1.dx 4e eru0.1 a1 p2.6 acmp1.i nn vadc0. g0ch0 orc4.ai n usic1_ ch1.dx 3e usic1_ ch1.dx 4e usic0_ ch0.dx 3e usic0_ ch0.d x4e usic0_ ch1.dx 5d eru0.2 a1 p2.7 acmp1.i np vadc0. g 1 ch1 orc5.ai n usic1_ ch1.dx 5e usic0_ ch0.dx 5c usic0_ ch1.dx 3d usic0_ ch1.dx 4d eru0.3 a1 p2.8 acmp0.i nn vadc0. g0ch1 vadc0. g1ch0 orc6.ai n usic0_ ch0.dx 3d usic0_ ch0.d x4d usic0_ ch1.dx 5c eru0.3 b1 p2.9 acmp0.i np vadc0. g0ch2 vadc0. g1ch4 orc7.ai n usic0_ ch0.dx 5a usic0_ ch1.dx 3b usic0_ ch1.dx 4b eru0.3 b0 p2.10 eru0.p dout1 ccu40. out2 eru0.g out1 ledts1 .col4 ccu80. out30 acmp0. out usic0_ ch1.do ut0 can.n1 _txd vadc0. g0ch3 vadc0. g1ch2 usic0_ ch0.dx 3c usic0_ ch0.d x4c usic0_ ch1.dx 0f can.n1 _rxde eru0.2 b0 p2.11 eru0.p dout0 ccu40. out3 eru0.g out0 ledts1 .col3 ccu80. ou t 31 usic0_ ch1.sc lkout usic0_ ch1.do ut0 can.n1 _txd acmp.r ef vadc0. g0ch4 vadc0. g1ch3 usic0_ ch1.dx 0e usic0_ ch1.dx 1e can.n1 _rxdf eru0.2 b1 p2.12 bccu0. out3 vadc0. emux00 usic1_ ch0.sc lkout usic1_ ch1.sc lkout acmp2. out usic1_ ch1.do ut0 ledts2 .col6 acmp3.i nn usic1_ ch0.dx 3a usic1_ ch0.d x4a usic1_ ch1.dx 0c usic1_ ch1.dx 1b eru1.3 a2 p2.13 bccu0. out4 ccu40. out3 usic1_ ch0.mc lkout ccu81. out31 vadc0. emux01 usic1_ ch1.do ut0 ccu81. out33 ccu41. out3 acmp3.i np usic1_ ch0.dx 5a usic1_ ch1.dx 0d eru1.3 a3 p3.0 bccu0. out0 usic1_ ch1.do ut0 usic1_ ch1.sc lkout ledts2 .cola ccu80. out21 acmp1. ou t us ic1_ ch0.se lo1 ccu81. out21 ccu41. out0 bccu0. trapin c ccu41.i n0aa ccu41.i n1aa ccu41.i n2aa ccu41.i n3aa ccu81.i n0aa ccu81.i n1aa ccu81. in2aa usic1_ ch1.dx 0e usic1_ ch1.dx 1d ccu81.i n3aa eru1.0 a1 p3.1 bccu0. out1 usic1_ ch1.do ut0 ledts2 .col0 ccu80. out20 acmp3. out usic1_ ch0.se lo0 ccu81. out20 ccu41. out1 usic1_ ch0.d x2f usic1_ ch1.dx 0f eru1.1 a1 table 9 port i/o functions (cont?d) function outputs inputs alt1 alt2 alt3 alt4 alt5 alt6 alt7 alt8 alt9 input input input input input input input input input input input input subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family data sheet 35 v1.2, 2016-08 p3.2 bccu0. out2 usic1_ ch1.sc lkout ledts2 .col1 ccu80. out11 acmp2. out usic1_ ch0.sc lkout ccu81. out11 ccu41. out2 usic1_ ch0.dx 3c usic1_ ch0.d x4c usic1_ ch1.dx 3d usic1_ ch1.dx 4d eru1.2 a1 p3.3 bccu0. out5 usic1_ ch0.do ut0 ledts2 .col2 ccu80. out10 acmp0. out usic1_ ch1.se lo0 ccu81. out10 ccu41. out3 usic1_ ch0.dx 0e usic1_ ch1.dx 2a eru1.1 a3 p3.4 bccu0. out6 usic1_ ch0.do ut0 usic1_ ch0.sc lkout ledts2 .col3 ccu80. out01 usic1_ ch1.mc lkout usic1_ ch1.se lo1 ccu81. out01 usic1_ ch0.dx 0f usic1_ ch0.d x1e usic1_ ch1.dx 2b eru1.2 a3 p4.0 bccu0. out0 eru1.p dout0 ledts2 .col5 eru1.g out0 ccu40. out0 acmp1. out usic1_ ch1.se lo1 ccu81. out10 ccu41. out0 ccu40.i n0ba ccu41.i n0ac ccu80.i n0au usic1_ ch 0 .dx 3d usic1_ ch0.d x4d p4.1 bccu0. out8 eru1.p dout1 ledts2 .col4 eru1.g out1 ccu40. out1 acmp3. out usic1_ ch1.se lo2 ccu81. out11 ccu41. out1 ccu40.i n1ba ccu41.i n1ac ccu80.i n1au posif1. in0b usic1_ ch0.dx 5c p4.2 bccu0. out4 eru1.p dout2 ccu81. out20 eru1.g out2 ccu40. out2 acmp2. out usic1_ ch1.se lo3 ccu81. out12 ccu41. out2 ccu40.i n2ba ccu41.i n2ac ccu80.i n2au ccu81.i n1ab posif1. in1b usic1_ ch0.dx 5d p4.3 bccu0. out5 eru1.p dout3 ccu81. out21 eru1.g out3 ccu40. out3 acmp0. out usic1_ ch0.sc lkout ccu81. out13 ccu41. out3 ccu40.i n3ba ccu41.i n3ac ccu80.i n3au posif1. in2b usic1_ ch0.d x1b p4.4 bccu0. ou t 0 ledts2 .line0 ledts1 .cola ccu80. out00 usic1_ ch0.do ut0 ccu81. out00 ccu41. out0 ccu41.i n0av usic1_ ch0.dx 0c usic1_ ch1.dx 5f eru1.0 a2 p4.5 bccu0. out8 ledts2 .line1 ledts1 .col6 ccu80. out01 usic1_ ch0.do ut0 usic1_ ch0.sc lkout ccu81. out01 ccu41. out1 ccu41.i n1av usic1_ ch0.dx 0d usic1_ ch0.d x1c eru1.1 a2 p4.6 bccu0. out2 ledts2 .line2 ccu81. out10 ledts1 .col5 ccu80. out10 usic1_ ch0.sc lkout ccu81. out02 ccu41. out2 ccu41.i n2av ccu81.i n0ab usic1_ ch0.d x1d eru1.2 a2 p4.7 bccu0. out5 ledts2 .line3 ccu81. out11 ledts1 .col4 ccu80. out11 usic1_ ch0.se lo0 ccu81. out03 ccu41. out3 ccu41.i n3av usic1_ ch0 . d x2a eru1.0 a3 p4.8 bccu0. out7 ledts2 .line4 ledts2 .col3 ledts1 .col3 ccu80. out30 ccu40. out0 usic1_ ch0.se lo1 ccu81. out30 can.n1 _txd ccu40.i n0av ccu41.i n0ba usic1_ ch0.d x2b can.n1 _rxdc p4.9 bccu0. out3 ledts2 .line5 ledts2 .col2 ledts1 .col2 ccu80. out31 ccu40. out1 usic1_ ch0.se lo2 ccu81. out31 can.n1 _txd ccu40.i n1av ccu41.i n1ba usic1_ ch0.d x2c can.n1 _rxdd table 9 port i/o functions (cont?d) function outputs inputs alt1 alt2 alt3 alt4 alt5 alt6 alt7 alt8 alt9 input input input input input input input input input input input input subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family data sheet 36 v1.2, 2016-08 p4.10 ledts2 .line6 ledts2 .col1 ledts1 .col1 ccu80. out00 ccu40. out2 usic1_ ch0.se lo3 ccu81. out32 ccu81. out00 bccu0. trapin d ccu40.i n2av ccu41.i n2ba ccu81.i n3ab usic1_ ch0.d x2d usic1_ ch1.dx 5a p4.11 ledts2 .line7 ledts2 .col0 ledts1 .col0 ccu80. out01 ccu40. out3 usic1_ ch0.se lo4 ccu81. out33 ccu81. out01 ccu40.i n3av ccu41.i n3ba usic1_ ch0.d x2e usic1_ ch1.dx 3a usic1_ ch1.dx 4a table 9 port i/o functions (cont?d) function outputs inputs alt1 alt2 alt3 alt4 alt5 alt6 alt7 alt8 alt9 input input input input input input input input input input input input subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family data sheet 37 v1.2, 2016-08 table 10 hardware i/o controlled functions function outputs outputs inputs inputs pull control pull control pull control pull control hwo0 hwo1 hwi0 hwi1 hw0_pd hw0_pu hw1_pd hw1_pu p0.0 ledts0. extended7 ledts0.tsin7 ledts0.tsin7 reserved for ledts scheme a: pull-down disabled always reserved for ledts scheme a: pull-down enabled always reserved for ledts scheme b: pull-up enabled and pull-down disabled, and vice versa p0.1 ledts0. extended6 ledts0.tsin6 ledts0.tsin6 p0.2 ledts0. extended5 ledts0.tsin5 ledts0.tsin5 p0.3 ledts0. extended4 ledts0.tsin4 ledts0.tsin4 p0.4 ledts0. extended3 ledts0.tsin3 ledts0.tsin3 p0.5 ledts0. extended2 ledts0.tsin2 ledts0.tsin2 p0.6 ledts0. extended1 ledts0.tsin1 ledts0.tsin1 p0.7 ledts0. extended0 ledts0.tsin0 ledts0.tsin0 p0.8 ledts1. extended0 ledts1.tsin0 ledts1.tsin0 p0.9 ledts1. extended1 ledts1.tsin1 ledts1.tsin1 p0.10 ledts1. extended2 ledts1.tsin2 ledts1.tsin2 p0.11 ledts1. extended3 ledts1.tsin3 ledts1.tsin3 p0.12 ledts1. extended4 ledts1.tsin4 ledts1.tsin4 p0.13 ledts1. extended5 ledts1.tsin5 ledts1.tsin5 p0.14 ledts1. extended6 ledts1.tsin6 ledts1.tsin6 p0.15 ledts1. extended7 ledts1.tsin7 ledts1.tsin7 p1.0 usic0_ch0.dout0 usic0_ch0.hwin0 bccu0.out2 bccu0.out2 p1.1 usic0_ch0.dout1 usic0_ch0.hwin1 bccu0.out3 bccu0.out3 p1.2 usic0_ch0.dout2 usic0_ch0.hwin2 bccu0.out4 bccu0.out4 subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family data sheet 38 v1.2, 2016-08 p1.3 usic0_ch0.dout3 usic0_ch0.hwin3 bccu0.out5 bccu0.out5 p1.4 bccu0.out6 bccu0.out6 p1.5 bccu0.out7 bccu0.out7 p1.6 bccu0.out8 bccu0.out8 p1.7 p1.8 p2.0 bccu0.out1 bccu0.out1 p2.1 bccu0.out6 bccu0.out6 p2.2 bccu0.out0 bccu0.out0 ccu40.out3 ccu40.out3 p2.3 acmp2.out acmp2.out p2.4 bccu0.out8 bccu0.out8 p2.5 acmp1.out acmp1.out p2.6 bccu0.out2 bccu0.out2 ccu40.out3 ccu40.out3 p2.7 bccu0.out8 bccu0.out8 ccu40.out3 ccu40.out3 p2.8 bccu0.out1 bccu0.out1 ccu40.out2 ccu40.out2 p2.9 bccu0.out7 bccu0.out7 ccu40.out2 ccu40.out2 p2.10 bccu0.out4 bccu0.out4 p2.11 bccu0.out5 bccu0.out5 p2.12 bccu0.out3 bccu0.out3 ccu41.out0 ccu41.out0 p2.13 bccu0.out4 bccu0.out4 ccu41.out2 ccu41.out2 p3.0 p3.1 usic1_ch0.dout3 usic1_ch0.hwin3 p3.2 usic1_ch0.dout2 usic1_ch0.hwin2 p3.3 usic1_ch0.dout1 usic1_ch0.hwin1 p3.4 usic1_ch0.dout0 usic1_ch0.hwin0 p4.0 p4.1 p4.2 p4.3 table 10 hardware i/o controlled functions function outputs outputs inputs inputs pull control pull control pull control pull control hwo0 hwo1 hwi0 hwi1 hw0_pd hw0_pu hw1_pd hw1_pu subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family data sheet 39 v1.2, 2016-08 p4.4 ledts2. extended0 ledts2.tsin0 ledts2.tsin0 reserved for ledts scheme a: pull-down disabled always reserved for ledts scheme a: pull-down enabled always reserved for ledts scheme b: pull-up enabled and pull-down disabled, and vice versa p4.5 ledts2. extended1 ledts2.tsin1 ledts2.tsin1 p4.6 ledts2. extended2 ledts2.tsin2 ledts2.tsin2 p4.7 ledts2. extended3 ledts2.tsin3 ledts2.tsin3 p4.8 ledts2. extended4 ledts2.tsin4 ledts2.tsin4 p4.9 ledts2. extended5 ledts2.tsin5 ledts2.tsin5 p4.10 ledts2. extended6 ledts2.tsin6 ledts2.tsin6 p4.11 ledts2. extended7 ledts2.tsin7 ledts2.tsin7 table 10 hardware i/o controlled functions function outputs outputs inputs inputs pull control pull control pull control pull control hwo0 hwo1 hwi0 hwi1 hw0_pd hw0_pu hw1_pd hw1_pu subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 40 v1.2, 2016-08 3 electrical parameter this section provides the electrical parame ter which are implementation-specific for the xmc1400. 3.1 general parameters 3.1.1 parameter interpretation the parameters listed in this section repres ent partly the characteristics of the xmc1400 and partly its requirements on the system. to aid interpreting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the ?symbol? column: ? cc such parameters indicate c ontroller c haracteristics, which ar e distinctive feature of the xmc1400 and must be regarded for a system design. ? sr such parameters indicate s ystem r equirements, which must be provided by the application system in which t he xmc1400 is designed in. subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 41 v1.2, 2016-08 3.1.2 absolute maximum ratings stresses above the values listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a st ress rating only and functional operation of the device at these or any ot her conditions above those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions may affect device reliability. table 11 absolute maximum rating parameters parameter symbol values unit note / test condition min. typ. max. junction temperature t j sr -40 ? 115 t st sr -40 ? 125 v ssp v ddp sr -0.3 ? 6 v ? voltage on any pin with respect to v ssp v in sr -0.5 ? v ddp + 0.5 or max. 6 v whichever is lower voltage on any analog input pin with respect to v ssp v ain sr -0.5 ? v ddp + 0.5 or max. 6 v whichever is lower input current on any pin during overload condition i in sr -10 ? 10 ma ? absolute sum of all input currents during overload condition | i in | sr -50 ? 50 ma ? analog comparator input voltage v cm sr -0.3 ? v ddp + 0.3 v subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 42 v1.2, 2016-08 3.1.3 pin reliability in overload when receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own io power supplies specification. table 12 defines overload conditions that will not cause any negative reliability impact if all the following conditions are met: ? full operation life-time is not exceeded ? operating conditions are met for ? pad supply levels ( v ddp ) ? temperature if a pin current is outside of the operating conditions but within the overload conditions, then the parameters of this pin as stated in t he operating conditions can no longer be guaranteed. operat ion is still possible in mo st cases but with relaxed parameters. note: an overload condition on one or more pins does not require a reset. note: a series resistor at the pin to limit the current to the maxi mum permitted overload current is sufficient to handle failur e situations like short to battery. figure 11 shows the path of the input currents during overload via the esd protection structures. the diodes against v ddp and ground are a simplified representation of these esd protection structures. table 12 overload parameters parameter symbol values unit note / test condition min. typ. max. input current on any port pin during overload condition i ov sr -5 ? 5 ma absolute sum of all input circuit currents during overload condition i ovs sr ? ? 25 ma subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 43 v1.2, 2016-08 figure 11 input overload current via esd structures table 13 and table 14 list input voltages that can be reached under overload conditions. note that the absolute maximum input voltages as defined in the absolute maximum ratings must not be exceeded during overload. table 13 pn-junction characteris itics for positive overload pad type i ov =5ma, t j =-40c i ov =5ma, t j = 115 c standard, high-current, an/dig_in v in = v ddp +0.5v v in = v ddp +0.5v table 14 pn-junction characterisitics for negative overload pad type i ov =5ma, t j =-40c i ov =5ma, t j = 115 c standard, high-current, an/dig_in v in = v ss -0.5v v in = v ss -0.5v pn.y i ovx gnd esd pad gnd v ddp v ddp subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 44 v1.2, 2016-08 3.1.4 operating conditions the following operating conditions must not be exceeded in order to ensure correct operation and reliability of the xmc1400. all parameters specified in the following tables refer to these operating condi tions, unless noted otherwise. table 15 operating conditions parameters parameter symbol values unit note / test condition min. typ. max. ambient temperature t a sr -40 ? ? chapter 3.3.2 . v ddp sr 1.8 ? i sc sr -5 ? i sc_d sr ?? subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 45 v1.2, 2016-08 3.2 dc parameters 3.2.1 input/output characteristics table 16 provides the characteristics of t he input/output pins of the xmc1400. note: these parameters are not subject to production test, but verified by design and/or characterization. note: unless otherwise stated, input dc and ac characteristics, including peripheral timings, assume that the input pads operate with the standard hysteresis. table 16 input/output characteristics (operating conditions apply) parameter symbol limit values unit test conditions min. max. output low voltage on port pins (with standard pads) v olp cc ? 1.0 v i ol = 11 ma (5 v) i ol = 7 ma (3.3 v) ?0.4v i ol = 5 ma (5 v) i ol = 3.5 ma (3.3 v) output low voltage on high current pads v olp1 cc ? 1.0 v i ol = 50 ma (5 v) i ol = 25 ma (3.3 v) ?0.32v i ol = 10 ma (5 v) ?0.4v i ol = 5 ma (3.3 v) output high voltage on port pins (with standard pads) v ohp cc v ddp - 1.0 ?v i oh = -10 ma (5 v) i oh = -7 ma (3.3 v) v ddp - 0.4 ?v i oh =-4.5ma (5v) i oh =-2.5ma (3.3v) output high voltage on high current pads v ohp1 cc v ddp - 0.32 ?v i oh = -6 ma (5 v) v ddp - 1.0 ?v i oh = -8 ma (3.3 v) v ddp - 0.4 ?v i oh = -4 ma (3.3 v) input low voltage on port pins (standard hysteresis) v ilps sr ? 0.19 v ddp v cmos mode (5 v, 3.3 v & 2.2 v) input high voltage on port pins (standard hysteresis) v ihps sr 0.7 v ddp ?vcmos mode (5 v, 3.3 v & 2.2 v) subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 46 v1.2, 2016-08 input low voltage on port pins (large hysteresis) v ilpl sr ? 0.08 v ddp v cmos mode (5 v, 3.3 v & 2.2 v) input high voltage on port pins (large hysteresis) v ihpl sr 0.85 v ddp ?vcmos mode (5 v, 3.3 v & 2.2 v) rise/fall time on high current pad 1) t hcpr , t hcpf cc ? 9 ns 50 pf @ 5 v 2) ? 12 ns 50 pf @ 3.3 v 3) ? 25 ns 50 pf @ 1.8 v 4) rise/fall time on standard pad 1) t r , t f cc ? 12 ns 50 pf @ 5 v 5) ? 15 ns 50 pf @ 3.3 v 6) . ? 31 ns 50 pf @ 1.8 v 7) . input hysteresis on port pin except p2.3 - p2.9 8) hys cc 0.08 v ddp ? v cmos mode (5 v), standard hysteresis 0.03 v ddp ? v cmos mode (3.3 v), standard hysteresis 0.02 v ddp ? v cmos mode (2.2 v), standard hysteresis 0.5 v ddp 0.75 v ddp v cmos mode(5 v), large hysteresis 0.4 v ddp 0.75 v ddp v cmos mode(3.3 v), large hysteresis 0.2 v ddp 0.65 v ddp v cmos mode(2.2 v), large hysteresis table 16 input/output characteristics (operating conditions apply) (cont?d) parameter symbol limit values unit test conditions min. max. subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 47 v1.2, 2016-08 input hysteresis on port pin p2.3 - p2.9 8) hys _ p2 cc 0.08 v ddp ? v cmos mode (5 v), standard hysteresis 0.03 v ddp ? v cmos mode (3.3 v), standard hysteresis 0.02 v ddp ? v cmos mode (2.2 v), standard hysteresis 0.35 v ddp 0.75 v ddp v cmos mode(5 v), large hysteresis 0.25 v ddp 0.75 v ddp v cmos mode(3.3 v), large hysteresis 0.15 v ddp 0.65 v ddp v cmos mode(2.2 v), large hysteresis pin capacitance (digital inputs/outputs) c io cc ? 10 pf pull-up current on port pins i pup cc ? -80 v ih,min (5 v) -95 ? v il,max (5 v) ?-50 v ih,min (3.3 v) -65 ? v il,max (3.3 v) pull-down current on port pins i pdp cc ? 40 v il,max (5 v) 95 ? v ih,min (5 v) ?30 v il,max (3.3 v) 60 ? v ih,min (3.3 v) input leakage current except p0.11 9) i ozp cc -1 1 v in < v ddp , t a i ozp1 cc -10 1 v in < v ddp , t a v ddp power off v po sr ? 0.3 v 10) maximum current per pin (excluding p1, v ddp and v ss ) i mp sr -10 11 ma ? maximum current per high currrent pins i mp1a sr -10 50 ma ? table 16 input/output characteristics (operating conditions apply) (cont?d) parameter symbol limit values unit test conditions min. max. subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 48 v1.2, 2016-08 maximum current into v ddp (vqfn64, lqfp64) i mvdd1 sr ? 520 ma maximum current into v ddp (vqfn48) i mvdd2 sr ? 390 ma maximum current into v ddp (vqfn40) i mvdd3 sr ? 260 ma maximum current out of v ss (vqfn64, lqfp64) i mvss1 sr ? 390 ma maximum current out of v ss (vqfn48) i mvss2 sr ? 260 ma maximum current out of v ss (vqfn40) i mvss3 sr ? 260 ma 1) rise/fall time parameters are taken with 10% - 90% of supply. 2) additional rise/fall time valid for c l =50pf-c l = 100 pf @ 0.150 ns/pf at 5 v supply voltage. 3) additional rise/fall time valid for c l =50pf-c l = 100 pf @ 0.205 ns/pf at 3.3 v supply voltage. 4) additional rise/fall time valid for c l =50pf-c l = 100 pf @ 0.445 ns/pf at 1.8 v supply voltage. 5) additional rise/fall time valid for c l =50pf-c l = 100 pf @ 0.225 ns/pf at 5 v supply voltage. 6) additional rise/fall time valid for c l =50pf-c l = 100 pf @ 0.288 ns/pf at 3.3 v supply voltage. 7) additional rise/fall time valid for c l =50pf-c l = 100 pf @ 0.588 ns/pf at 1.8 v supply voltage. 8) hysteresis is implemented to avoi d meta stable states and switching due to internal ground bounce. it cannot be guaranteed that it suppresses switching due to external system noise. 9) an additional error current ( i inj ) will flow if an overload current flows through an adjacent pin. 10) however, for applications with strict low power-down current requirements, it is mandatory that no active voltage source is supplied at any gpio pin when v ddp is powered off. table 16 input/output characteristics (operating conditions apply) (cont?d) parameter symbol limit values unit test conditions min. max. subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 49 v1.2, 2016-08 3.2.2 analog to digital converters (adc) table 17 shows the analog to digital converter (adc) characteristics. note: these parameters are not subject to production test, but verified by design and/or characterization. table 17 adc characteristics (o perating conditions apply) 1) parameter symbol values unit note / test condition min. typ. max. supply voltage range (internal reference) v dd_int sr 2.0 ? 3.0 v shscfg.aref = 11 b ; calctr.calgnstc = 0c h for f sh = 32 mhz, 12 h for f sh = 48 mhz 3.0 ? 5.5 v shscfg.aref = 10 b supply voltage range (external reference) v dd_ext sr 3.0 ? 5.5 v shscfg.aref = 00 b analog input voltage range v ain sr v ssp - 0.05 ? v ddp + 0.05 v auxiliary analog reference ground 2) v refgnd sr v ssp - 0.05 ?1.0vg0ch0 v ssp - 0.05 ?0.2vg1ch0 internal reference voltage (full scale value) v refint cc 5v switched capacitance of an analog input c ains cc ? 1.2 2 pf gnctrxz.gainy = 00 b (unity gain) ? 1.2 2 pf gnctrxz.gainy = 01 b (gain g1) ? 4.5 6 pf gnctrxz.gainy = 10 b (gain g2) ? 4.5 6 pf gnctrxz.gainy = 11 b (gain g3) total capacitance of an analog input c aint cc ? ? 10 pf total capacitance of the reference input c areft cc ? ? 10 pf subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 50 v1.2, 2016-08 gain settings g in cc 1 ? gnctrxz.gainy = 00 b (unity gain) 3 ? gnctrxz.gainy = 01 b (gain g1) 6 ? gnctrxz.gainy = 10 b (gain g2) 12 ? gnctrxz.gainy = 11 b (gain g3) sample time t sample cc 5??1 / f adc v dd = 5.0 v, f adci = 48 mhz 3??1 / f adc v dd = 5.0 v, f adci = 32 mhz 3??1 / f adc v dd = 3.3 v, f adci = 32 mhz 30 ? ? 1 / f adc v dd = 2.0 v, f adci = 32 mhz conversion time in fast compare mode t cf cc 9 1 / f adc 3) conversion time in 12-bit mode t c12 cc 20 1 / f adc 3) maximum sample rate in 12-bit mode 4) f c12 cc ? ? f adc / 42.5 ?1 sample pending ?? f adc / 62.5 ?2 samples pending conversion time in 10-bit mode t c10 cc 18 1 / f adc 3) maximum sample rate in 10-bit mode 4) f c10 cc ? ? f adc / 40.5 ?1 sample pending ?? f adc / 58.5 ?2 samples pending conversion time in 8-bit mode t c8 cc 16 1 / f adc 3) table 17 adc characteristics (o perating conditions apply) 1) (cont?d) parameter symbol values unit note / test condition min. typ. max. subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 51 v1.2, 2016-08 maximum sample rate in 8-bit mode 4) f c8 cc ? ? f adc / 38.5 ?1 sample pending ?? f adc / 54.5 ?2 samples pending rms noise 5) en rms cc ?1.5?lsb 12 dc input, shscfg.aref = 00 b , gnctrxz.gainy = 00 b (unity gain), v dd = 5.0 v, v ain = 2.5 v, 25 ea dnl cc ? 2.0 ? lsb 12 inl error ea inl cc ? 4.0 ? lsb 12 gain error with external reference ea gain cc ? 0.5 ? % shscfg.aref = 00 b (calibrated) gain error with internal reference 6) ea gain cc ? 3.6 ? % shscfg.aref = 1x b (calibrated), -40 ea off cc ? 8.0 ? mv calibrated, v dd = 5.0 v 1) the parameters are defined for adc clock frequencies f sh = 32 mhz for the full supply range, and f sh = 48 mhz at v dd_int , v dd_ext = 5 v. usage of any other frequencies may affect the adc performance. 2) the alternate reference ground connection is separate fo r each converter. this mode, therefore, provides the lowest noise impact. 3) no pending samples assumed, excluding sampling time and calibration. 4) includes synchronization and calibration (average of gain and offset calibration). 5) this parameter can also be defined as an snr value: snr[db] = 20 log( a maxeff / n rms ). with a maxeff = 2 n / 2, snr[db] = 20 log ( 2048 / n rms ) [n = 12]. n rms = 1.5 lsb12, therefore, equals snr = 20 log (2048 / 1.5) = 62.7 db. 6) includes error from the reference voltage. table 17 adc characteristics (o perating conditions apply) 1) (cont?d) parameter symbol values unit note / test condition min. typ. max. subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 52 v1.2, 2016-08 figure 12 adc voltage supply mc_vadc_arefpaths aref : v agnd sar converter v cal vss vdd internal reference refsel 0 1 00 1x v dd ch7 . . ch0 v ddint / v ddext v ain v refgnd v refint chnr v aref v ref subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 53 v1.2, 2016-08 3.2.3 out of range comparator (orc) characteristics the out-of-range comparator (orc) tr iggers on analog input voltages ( v ain ) above v ddp on selected input pins (orcx.ain) and generates a service request trigger (orcx.out). note: these parameters are not subject to production test, but verified by design and/or characterization. figure 13 orcx.out trigger generation table 18 out of range comparator (orc) characteristics (operating conditions apply; v ddp = 3.0 v - 5.5 v; c l = 0.25pf) parameter symbol values unit note / test condition min. typ. max. dc switching level v odc cc ?? v ain v ddp + v odc hysteresis v ohys cc 15 ? t opdd cc 103 ?? v ain v ddp + 150 mv 88 ?? v ain v ddp + 350 mv never detected overvoltage pulse t opdn cc ?? v ain v ddp + 150 mv ?? v ain v ddp + 350 mv detection delay t odd cc 39 ? v ain v ddp + 150 mv 31 ? v ain v ddp + 350 mv release delay t ord cc 44 ? v ain v ddp ; v ddp = 5 v 57 ? v ain v ddp ; v ddp = 3.3 v enable delay t oed cc ?? v ss v ddp t ord v odc v ohys t odd orcx . out orcx . ain subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 54 v1.2, 2016-08 figure 14 orc detection ranges v ain (v) v ssa v ddp + 350 mv t v ddp + 150 mv overvolt age may be det ect ed (long enough, level uncert ain ) never detected overvoltage pulse (too short) t < t op dn t op dn < t < t op dd overvolt age may be detected t > t opdd always detected overvolt age pulse t < t opdn never detected overvolt age pulse (too short) t opdn < t < t op dd t > t op dd always det ect ed overvolt age pulse v ddp + 60 mv overvolt age may be det ect ed t > t op dd never detected overvolt age pulse (too low) v ddp subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 55 v1.2, 2016-08 3.2.4 analog comparator characteristics table 19 below shows the analog comparator characteristics. note: these parameters are not subject to production test, but verified by design and/or characterization. table 19 analog comparator characteristics (operating conditions apply) parameter symbol limit values unit notes/ test conditions min. typ. max. input voltage v cmp sr -0.05 ? v ddp + 0.05 v input offset v cmpoff cc ? +/-3 ? mv high power mode v cmp < 200 mv propagation delay 1) 1) total analog comparator delay is the sum of propagation delay and filter delay. t pdelay cc ? 25 ? ns high power mode, v cmp = 100 mv ? 80 ? ns high power mode, v cmp = 25 mv ? 250 ? ns low power mode, v cmp = 100 mv ? 700 ? ns low power mode, v cmp = 25 mv current consumption i acmp cc ? 100 ? v cmp > 30 mv ?66? v cmp > 30 mv ?10? v hys cc ? +/-15 ? mv filter delay 1) t fdelay cc ? 5 ? ns subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 56 v1.2, 2016-08 3.2.5 temperature sensor characteristics note: these parameters are not subject to production test, but verified by design and/or characterization. table 20 temperature sensor characteristics parameter symbol values unit note / test condition min. typ. max. measurement time t m cc ?? t sr sr -40 ? t tsal cc -6 ? 6 c t j > 20c -10 ? 10 c 0c t j ? t j < 0c start-up time t tsst sr ?? subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 57 v1.2, 2016-08 3.2.6 oscillator pins note: it is strongly recomm ended to measure the oscill ation allowance (negative resistance) in the final target system (layout) to determine th e optimal parameters for the oscillator operation. please refer to the limits specified by the crystal or ceramic resonator supplier. note: these parameters are not subject to production test, but verified by design and/or characterization. the oscillator pins can be operated wit h an external crystal/resonator (see figure 15 ) or in direct input mode (see figure 16 ). figure 15 oscillator in crystal mode xtal1 xtal2 f os c damping resistor may be needed for some crystals v ppx v ppx_min v ppx v ppx_max t v v ppx_min t os cs gnd subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 58 v1.2, 2016-08 figure 16 oscillator in direct input mode v v ihbx_max v ss t i n p u t h i g h v o l t a g e i n p u t l o w v o l t a g e i n p u t h i g h v o l t a g e xtal1 xtal2 not connected external clock source direct input mode v ihbx_min v ilbx_max v ilbx_min subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 59 v1.2, 2016-08 table 21 osc_xtal parameters parameter symbol values unit note / test condition min. typ. max. input frequency f osc sr 4 ? ? t oscs is defined from the moment the oscillator is enabled wih scu_anaoschpctrl.mode until the oscillations reach an amplitude at xtal1 of 0.9 * v ppx . 2) the external oscillator circuitry must be optimized by the customer and checked for negative resistance and amplitude as recommended and specified by crystal suppliers. t oscs cc ?? v ix sr -0.3 ? ? v ppx sr 0.6 ? subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 60 v1.2, 2016-08 table 22 rtc_xtal parameters parameter symbol values unit note / test condition min. typ. max. input frequency f osc sr ? ? t oscs is defined from the moment the oscillator is enabled by the user with scu_anaosclpctrl.mode until the oscillations reach an amplitude at rtc_xtal1 of 0.9 * v ppx . 2) the external oscillator circuitry must be optimized by the customer and checked for negative resistance and amplitude as recommended and specified by crystal suppliers. t oscs cc ?? v ix sr -0.3 ? v ppx sr 0.2 ? subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 61 v1.2, 2016-08 3.2.7 power supply current the total power supply current defined belo w consists of a leakage and a switching component. application relevant values are typically lowe r than those given in the following tables, and depend on the customer's system operat ing conditions (e.g. thermal connection or used application configurations). note: these parameters are not subject to production test, but verified by design and/or characterization. table 23 power supply parameter table; v ddp = 5v parameter symbol values unit note / test condition min. typ. 1) max. active mode current peripherals enabled f mclk / f pclk i ddpae cc ? ? ? ? ? ? ? / ? ? f mclk / f pclk i ddpad cc ? ? ? ? ? ? ? / ? ? f mclk / f pclk i ddpar cc ? ? f mclk / f pclk i ddpse cc ? ? ? ? ? ? ? ? / ? ? subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 62 v1.2, 2016-08 sleep mode current peripherals clock disabled flash active f mclk / f pclk i ddpsd cc ? ? ? ? ? ? ? ? / ? ? f mclk / f pclk i ddpsr cc ? ? ? ? ? ? ? ? / ? ? i ddpds cc ? ? t ssa cc ? ? t dsa cc ? ? t a =+25 v ddp =5v. 2) cpu and all peripherals clock enabled, flash is in active mode. 3) cpu enabled, all peripherals clock disabled, flash is in active mode. 4) cpu in sleep, all peripherals clock enabled and flash is in active mode. 5) cpu in sleep, flash is in active mode. 6) cpu in sleep, flash is powered down and code executed from ram after wake-up. 7) cpu in sleep, peripherals clock disabled, flash is powered down and code executed from ram after wake-up. 8) cpu in sleep, flash is in active mode during sleep mode. 9) cpu in sleep, flash is in powered down mode during deep sleep mode. table 23 power supply parameter table; v ddp = 5v parameter symbol values unit note / test condition min. typ. 1) max. subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 63 v1.2, 2016-08 figure 17 shows typical graphs for active mode supply current for v ddp = 5 v, v ddp = 3.3 v, v ddp = 1.8 v across different clock frequencies. figure 17 active mode, a) peripherals cl ocks enabled, b) peripherals clocks disabled: supply current i ddpa over supply voltage v ddp for different clock frequencies condition: 1. ta = +25 c 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 1/1 8/16 16/32 24/48 48/96 i ? (ma) mclk ? / ? pclk ? (mhz) iddpae ? 5v ? / ? 3.3v iddpae ? 1.8v iddpad ? 5v ? / ? 3.3v ?? /1.8v subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 64 v1.2, 2016-08 figure 18 shows typical graphs for sleep mode current for v ddp = 5 v, v ddp = 3.3 v, v ddp = 1.8 v across different clock frequencies. figure 18 sleep mode, peripherals clocks disabled, flash powered down: supply current i ddpsd over supply voltage v ddp for different clock frequencies condition: 1. ta = +25 c 0.0 0.5 1.0 1.5 2.0 2.5 1/1 8/16 16/32 24/48 32/64 i ? (ma) mclk ? / ? pclk ? (mhz) iddpsr ? 5v ? / ? 3.3v ? / ? 1.8v subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 65 v1.2, 2016-08 table 24 provides the active current consumpt ion of some modules operating at 5 v power supply at 25 table 24 typical active current parameter table active current consumption symbol limit values unit test condition typ. baseload current i cpuddc 4.14 ma modules including core, scu, port, memories, anatop 1) 1) baseload current is measured with device running in user mode, mclk=pclk=48 mhz, with an endless loop in the flash memory. the clock to the modules stated in cgatstat0 are gated. vadc and shs i adcddc 3.73 ma set cgatclr0.vadc to 1 2) 2) active current is measured with: module enabled, mclk=48 mhz, running in auto-scan conversion mode usicx i usic0ddc 1.35 ma set cgatclr0.usic0 to 1 3) 3) active current is measured with: module enabled, each of the 2 usic channels sending alternate messages at 57.6 kbaud every 200 ms ccu4x i ccu40ddc 0.99 ma set cgatclr0.ccu40 to 1 4) 4) active current is measured wi th: module enabled, mclk=pclk=48 mhz, 1 ccu4 slice for pwm switching at 20khz with duty cycle varying at 10%-90%, 1 ccu4 slic e in capture mode for reading period and duty cycle ccu8x i ccu80ddc 1.00 ma set cgatclr0.ccu80 to 1 5) 5) active current is measured with: module enabled, mclk=pclk=48 mhz, 3 ccu8 slices with pwm frequency at 20khz and a period match interrupt used to toggle duty cycle between 10% and 90% posifx i pif0ddc 1.05 ma set cgatclr0.posif0 to 1 6) 6) active current is measured with: module enabl ed, mclk=48 mhz, pclk=96 mhz, hall sensor mode ledtsx i ltsxddc 1.14 ma set cgatclr0.ledtsx to 1 7) 7) active current is measured with: module enabled, mclk=48 mhz, 1 led column, 6 led/ts lines, pad scheme a with large pad hysteresis c onfig, time slice duration = 1.048 ms bccu0 i bccu0ddc 0.29 ma set cgatclr0.bccu0 to 1 8) 8) active current is measured with: module enabled, mclk=48 mhz, pclk=96mhz, fclk=0.8 mhz, normal mode (bccu clock = fclk/4), 4 bccu channels with packers enabled and 1 dimming engine, change color or dim every 1s math i mathddc 0.50 ma set cgatclr0.math to 1 9) 9) active current is measured with: module enabled, mclk=48 mhz, pclk=96 mhz, tangent calculation in while loop; cordic circular rotation, no keep, autostart; 32-by-32 bit signed div, autostart, dvs right shift by 11 wdt i wdtddc 0.03 ma set cgatclr0.wdt to 1 10) rtc i rtcddc 0.01 ma set cgatclr0.rtc to 1 11) multican i mcanddc 1.38 ma set cgatclr0.mcan0 to 1 12) subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 66 v1.2, 2016-08 10) active current is measured with: module enabled, mclk=48 mhz, time-out mode; wlb = 0, wub = 0x00008000; wdt serviced every 1 s 11) active current is measured with: module enabled, mclk=48 mhz, periodic interrupt enabled 12) active current is measured with: module enabled , mclk=48 mhz, running at 20 mhz baudrate generator, 1 node activated, 1 transmit and 1 receive object active. subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 67 v1.2, 2016-08 3.2.8 flash memory parameters note: these parameters are not subject to production test, but verified by design and/or characterization. table 25 flash memory parameters parameter symbol values unit note / test condition min. typ. max. erase time per page / sector t erase cc 6.8 7.1 7.6 ms program time per block t pser cc 102 152 204 t wu cc ? ? t a cc ? ? t ret cc 10 ?? n wsflash cc 0 0 0 f mclk = f mclk = f mclk = f mclk = n ecyc cc ?? n tecyc cc ?? subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 68 v1.2, 2016-08 figure 19 logical structure of the flash word 0 word 1 word 2 word 3 sector 1 sector n_log_sec-1 page 0 page 1 page 15 page 14 page 13 1 sector = 16 pages = 4 kb sector 0 data block 0 data block 1 data block 14 data block 15 1 page = 16 data blocks = 256 bytes 1 block = 4 words = 16 bytes data block 2 nvm n_log_sec 1) * 4 kb 1) the number of sectors, n_log_sec, depends on the flash memory size of the product derivative . subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 69 v1.2, 2016-08 3.3 ac parameters 3.3.1 testing waveforms figure 20 rise/fall time parameters figure 21 testing waveform, output delay figure 22 testing waveform, output high impedance 10 % 90% v ss v ddp t r t f 10% 90% v ddp / 2 v ddp / 2 v ddp v ss test points v load + 0.1v timing reference points v load -0.1v v oh -0.1v v ol + 0.1v subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 70 v1.2, 2016-08 3.3.2 power-up and supply threshold characteristics table 26 provides the characteristics of the supply threshold in xmc1400. the guard band between the lowest valid o perating voltage and the brownout reset threshold provides a margin for noise immunity and hysteresis. the electrical parameters may be violated while v ddp is outside its operating range. the brownout detection triggers a reset wit hin the defined range. the prewarning detection can be used to trigger an early wa rning and issue corrective and/or fail-safe actions in case of a critical supply voltage drop. note: these parameters are not subject to production test, but verified by design and/or characterization. table 26 power-up and supply threshold parameters (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. v ddp ramp-up time t rampup sr v ddp / s vddprise ? v ddp slew rate s vddpop sr 0 ? s vddp10 sr 0 ? v ddp s vddprise sr 0 ? s vddpfall 1) sr 0 ? v ddp prewarning voltage v ddppw cc 2.1 2.25 2.4 v anavdel.vdel_ select = 00 b 2.85 3 3.15 v anavdel.vdel_ select = 01 b 4.2 4.4 4.6 v anavdel.vdel_ select = 10 b subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 71 v1.2, 2016-08 figure 23 supply threshold parameters v ddp brownout reset voltage v ddpbo cc 1.55 1.62 1.75 v calibrated, before user code starts running v ddp voltage to ensure defined pad states v ddppa cc ? ? t ssw sr ? t bmi sr ? v ddp and v ssp to fulfill the requirement as stated for this parameter. 2) valid for a 100 nf buffer capacitor connected to supp ly pin where current from capacitor is forwarded only to the chip. a larger capacitor value has to be chosen if the power source sink a current. 3) this values does not include the ramp-up time. during star tup firmware execution, mclk is running at 48 mhz and the clocks to peripheral as specif ied in register cgatstat0 are gated. table 26 power-up and supply threshold parameters (operating conditions apply) (cont?d) parameter symbol values unit note / test condition min. typ. max. vddp } 5.0v v ddppw v ddpbo subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 72 v1.2, 2016-08 3.3.3 on-chip oscillator characteristics table 27 provides the characteristics of the 96 mhz digital controlled oscillator dco1. note: these parameters are not subject to production test, but verified by design and/or characterization. table 28 provides the characteristics of the 32 khz digital controlled oscillator dco2. table 27 96 mhz dco1 characteristics (operating conditions apply) parameter symbol limit values unit test conditions min. typ . max. nominal frequency f nom cc ? 96 ? mhz under nominal conditions 1) after trimming 1) the deviation is relative to the factory trimmed frequency at nominal v ddc and t a =+25 f ltx cc -0.3 ? 0.3 % with respect to f nom (typ), over temperature (-40 f lt cc -1.7 ? 3.4 % with respect to f nom (typ), over temperature (0 f nom (typ), over temperature (-40 table 28 32 khz dco2 characteristi cs (operating conditions apply) parameter symbol limit values unit test conditions min. typ. max. nominal frequency f nom cc ? 32.75 ? khz under nominal conditions 1) after trimming 1) the deviation is relative to the factory trimmed frequency at nominal v ddc and t a =+25 f lt cc -1.7 ? 3.4 % with respect to f nom (typ), over temperature (0 f nom (typ), over temperature (-40 subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 73 v1.2, 2016-08 3.3.4 serial wire debug port (sw-dp) timing the following parameters are applicable for communication through the sw-dp interface. note: these parameters are not subject to production test, but verified by design and/or characterization. figure 24 swd timing table 29 swd interface timing parameters (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. swdclk high time t 1 sr 50 ? 500000 ns ? swdclk low time t 2 sr 50 ? 500000 ns ? swdio input setup to swdclk rising edge t 3 sr 10 ? ? ns ? swdio input hold after swdclk rising edge t 4 sr 10 ? ? ns ? swdio output valid time after swdclk rising edge t 5 cc ? ? 68 ns c l =50pf ??62nsc l =30pf swdio output hold time from swdclk rising edge t 6 cc 4 ? ? ns swdclk swdio (output ) t 1 t 2 t 6 t 5 swdio (input ) t 3 t 4 subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 74 v1.2, 2016-08 3.3.5 spd timing requirements the optimum spd decision time between 0 b and 1 b is 0.75 s. with this value the system has maximum robustness against frequency deviations of the sampling clock on tool and on device side. however it is not always possible to exactly match this value with the given constraints for the sample clock. for instance for a oversampling rate of 4, the sample clock will be 8 mhz and in this case the closest possible effective decision time is 5.5 clock cycles (0.69 s). for a balanced distribution of the timing ro bustness of spd between tool and device, the timing requirements for the tool are: ? frequency deviation of the sample clock is +/- 5% ? effective decision time is between 0. 69 s and 0.75 s (calculated with nominal sample frequency) table 30 optimum number of sample clocks for spd sample freq. sampling factor sample clocks 0 b sample clocks 1 b effective decision time 1) 1) nominal sample frequency period multiplied with 0.5 + (max. number of 0 b sample clocks) remark 8 mhz 4 1 to 5 6 to 12 0.69 s the other closest option (0.81 s) for the effective decision time is less robust. subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 75 v1.2, 2016-08 3.3.6 peripheral timings note: these parameters are not subject to production test, but verified by design and/or characterization. 3.3.6.1 synchronous serial in terface (usic ssc) timing the following parameters are applicable for a usic channel operated in ssc mode. note: operating conditions apply. table 31 usic ssc master mode timing parameter symbol values unit note / test condition min. typ. max. sclkout master clock period t clk cc 4/ mclk ?? t 1 cc t clk /2 - 28 ?? t 2 cc 0 ?? t 3 cc -28 ? t 4 sr 75 ?? t 5 sr 0 ?? table 32 usic ssc slave mode timing parameter symbol values unit note / test conditio n min. typ. max. dx1 slave clock period t clk sr 4/ mclk ?? t 10 sr 16 ?? subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 76 v1.2, 2016-08 select input dx2 hold after last clock input dx1 receive edge 1) t 11 sr 17 ?? t 12 sr 21 ?? t 13 sr 15 ?? t 14 cc - ? table 32 usic ssc slave mode timing parameter symbol values unit note / test conditio n min. typ. max. subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 77 v1.2, 2016-08 figure 25 usic - ssc master/slave mode timing note: this timing diagram shows a standard configuration, for which the slave select signal is low-active, and the serial clock signal is not shifted and not inverted. t 2 t 1 usic_ssc_tmgx.vsd clock output sclkout data output dout[3:0] t 3 t 3 t 5 data valid t 4 fi rs t trans mi t edge data input dx0/dx[5:3] select output selox active master mode timing slave mode timing t 11 t 10 clock input dx1 data output dout[3:0] t 14 t 14 data valid data input dx0/dx[5:3] select input dx2 active t 13 t 12 transmit edge: with this clock edge , transmit data is shifted to transmit data output . receive edge: with this clock edge , receive data at receive data input is latched . receive edge last receive edge inactive inactive transmit edge inactive inactive first transmit edge receive edge transmit edge last receive edge t 5 data valid t 4 data valid t 12 t 13 drawn for brgh .sclkcfg = 00 b . also valid for for sclkcfg = 01 b with inverted sclkout signal. subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 78 v1.2, 2016-08 3.3.6.2 inter-ic (iic) interface timing the following parameters are applicable fo r a usic channel operated in iic mode. note: operating conditions apply. table 33 usic iic standard mode timing 1) 1) due to the wired-and configuration of an iic bus system, the port drivers of the scl and sda signal lines need to operate in open-drain mode. the high level on these lines must be held by an external pull-up device, approximalely 10 kohm for operation at 100 kbit/s, approximately 2 kohm for operation at 400 kbit/s. parameter symbol values unit note / test condition min. typ. max. fall time of both sda and scl t 1 cc/sr --300ns rise time of both sda and scl t 2 cc/sr - - 1000 ns data hold time t 3 cc/sr 0- - s data set-up time t 4 cc/sr 250 - - ns low period of scl clock t 5 cc/sr 4.7 - - s high period of scl clock t 6 cc/sr 4.0 - - s hold time for (repeated) start condition t 7 cc/sr 4.0 - - s set-up time for repeated start condition t 8 cc/sr 4.7 - - s set-up time for stop condition t 9 cc/sr 4.0 - - s bus free time between a stop and start condition t 10 cc/sr 4.7 - - s capacitive load for each bus line c b sr - - 400 pf subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 79 v1.2, 2016-08 table 34 usic iic fast mode timing 1) 1) due to the wired-and configuration of an iic bus system, the port drivers of the scl and sda signal lines need to operate in open-drain mode. the high level on these lines must be held by an external pull-up device, approximalely 10 kohm for operation at 100 kbit/s, approximately 2 kohm for operation at 400 kbit/s. parameter symbol values unit note / test condition min. typ. max. fall time of both sda and scl t 1 cc/sr 20 + 0.1*c b 2) 2) c b refers to the total capacitance of one bus line in pf. -300ns rise time of both sda and scl t 2 cc/sr 20 + 0.1*c b -300ns data hold time t 3 cc/sr 0- - s data set-up time t 4 cc/sr 100 - - ns low period of scl clock t 5 cc/sr 1.3 - - s high period of scl clock t 6 cc/sr 0.6 - - s hold time for (repeated) start condition t 7 cc/sr 0.6 - - s set-up time for repeated start condition t 8 cc/sr 0.6 - - s set-up time for stop condition t 9 cc/sr 0.6 - - s bus free time between a stop and start condition t 10 cc/sr 1.3 - - s capacitive load for each bus line c b sr - - 400 pf subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 80 v1.2, 2016-08 figure 26 usic iic timing 3.3.6.3 inter-ic sound (iis) interface timing the following parameters are applicable for a usic channel operated in iis mode. note: operating conditions apply. table 35 usic iis master transmitter timing parameter symbol values unit note / test condition min. typ. max. clock period t 1 cc 4/ f mclk --ns clock high t 2 cc 0.35 x t 1min --ns clock low t 3 cc 0.35 x t 1min --ns hold time t 4 cc 0 - - ns clock rise time t 5 cc - - 0.15 x t 1min ns scl sda scl sda t 1 t 2 t 1 t 2 t 10 t 9 t 7 t 8 t 7 t 3 t 4 t 5 t 6 ps sr s 70% 30 % 9 th clock 9 th clock subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family electrical parameter data sheet 81 v1.2, 2016-08 figure 27 usic iis master transmitter timing figure 28 usic iis slave receiver timing table 36 usic iis slave receiver timing parameter symbol values unit note / test condition min. typ. max. clock period t 6 sr 4/ f mclk --ns clock high t 7 sr 0.35 x t 6min --ns clock low t 8 sr 0.35 x t 6min --ns set-up time t 9 sr 0.3 x t 6min --ns hold time t 10 sr 15 - - ns sck wa/ dout t 1 t 5 t 3 t 2 t 4 sck wa/ din t 6 t 10 t 8 t 7 t 9 subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family package and reliability data sheet 82 v1.2, 2016-08 4 package and reliability the xmc1400 is a member of the xmc ? 1000 family of microcontrollers. it is also compatible to a certain extent with me mbers of similar families or subfamilies. each package is optimized for the device it houses. therefore, there may be slight differences between packages of the same pi n-count but for different device types. in particular, the size of the exposed die pad may vary. if different device types are considered or planned for an applicati on, it must be ensured that the board layout fits all packages under consideration. 4.1 package parameters table 37 provides the thermal characteristi cs of the packages used in xmc1400. note: for electrical reasons, it is required to connect the exposed pad to the board ground v ssp , independent of emc and thermal requirements. 4.1.1 thermal considerations when operating the xmc1400 in a system, the to tal heat generated in the chip must be dissipated to the ambient environment to pr event overheating and the resulting thermal damage. the maximum heat that can be dissipated dep ends on the package and its integration into the target board. the ?thermal resistance r table 37 thermal characteristics of the packages parameter symbol limit values unit package types min. max. exposed die pad dimensions ex r subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family package and reliability data sheet 83 v1.2, 2016-08 the difference between junction temperature and ambient temperature is determined by p int + p iostat + p iodyn ) r p int = v ddp i ddp (switching current and leakage current). the static external power consumption caus ed by the output drivers is defined as p iostat = v ddp - v oh ) i oh ) + v ol i ol ) the dynamic external power consumpt ion caused by the output drivers ( p iodyn ) depends on the capacitive load connected to the resp ective pins and their switching frequencies. if the total power di ssipation for a given system configur ation exceeds the defined limit, countermeasures must be taken to ensure proper system operation: ? reduce v ddp , if possible in the system ? reduce the system frequency ? reduce the number of output pins ? reduce the load on active output drivers subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family package and reliability data sheet 84 v1.2, 2016-08 4.2 package outlines figure 29 pg-tssop-38-9 subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family package and reliability data sheet 85 v1.2, 2016-08 figure 30 pg-vqfn-40-17 figure 31 pg-vqfn-48-73 0.05 max. standoff 40x coplanarity 0.9 max. (0.2) seating plane c 0.08 c 0.1 c 9 x 0.4 = 3.6 0.4 0.4 0.05 40x b m ac 0.05 0.07 m c 0.05 0.2 b m ac 0.05 b m ac 0.05 10 1 21 30 11 20 40 31 0.1 3.6 index marking 0.1 3.6 b index marking a 5 5 0.1 ac 2x 0.1 b c 2x pg-vqfn-40-13, -14, -17-po v05 pg-vqfn-48-35, -73-po v04 index marking 0.9 max. 0.1 c 48x 0.05 c coplanarity (0.203) seating plane c 0.05 max. stand off 11 x 0.5 = 5.5 0.5 0.4 0.05 0.1 4.1 0.1 b m ac 0.1 b m ac 0.1 4.1 0.1 48x b m ac 0.05 m c +0.05 -0.07 0.25 7 a 0.1 a 2x b 7 0.1 b 2x index marking 1 12 13 48 24 37 25 36 subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family package and reliability data sheet 86 v1.2, 2016-08 figure 32 pg-lqfp-64-26 d 12 h 0.2 a-b d 4x a-b0.2 64x 64xc dc b 12 1 64 index marking 0.5 0.05 0.22 0.08 m a-b d c 0.08 0.05 0.1 0.05 1.4 1.6 max. 0.15 0.6 h a -0.06 +0.05 0.15 64x c 10 1) 2) 10 1) pg-lqfp-64-10, -21, -26-po v03 15 x 0.5 = 7.5 coplanarity seating plane stand off 0...7 1) does not include plastic or metal protrusion of 0.25 max. per side 2) does not include dambar protrusion of 0.08 max. per side subject to agreement on the use of product information xmc ? 1400 aa-step xmc ? 1000 family quality declaration data sheet 87 v1.2, 2016-08 figure 33 pg-vqfn-64-6 all dimensions in mm. 5 quality declaration table 38 shows the characteristics of the quality parameters in the xmc1400. table 38 quality parameters parameter symbol limit values unit notes min. max. esd susceptibility according to human body model (hbm) v hbm sr - 2000 v conforming to eia/jesd22- a114-b esd susceptibility according to charged device model (cdm) pins v cdm sr - 500 v conforming to jesd22-c101-c moisture sensitivity level msl cc -3-jedec j-std-020d soldering temperature t sdr sr - 260 c profile according to jedec j-std-020d pg-vqfn-64-6-po v04 0.1 4.5 0.1 b m ac 8 a 0.1 a c 2x b 8 0.1 bc 2x index marking 0.9 max. 0.1 c (0.2) 64x 0.08 c coplanarity seating plane c 0.05 max. stand off index marking 0.4 0.05 0.07 64x b m ac 0.05 m c 0.05 0.2 15 x 0.4 = 6 0.4 0.1 b m ac 0.1 4.5 17 1 16 64 32 49 33 48 subject to agreement on the use of product information www.infineon.com published by infineon technologies ag |
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